A variety of circuits are included in integrated circuits, such as memory devices. One such circuit is a delay lock loop (“DLL”), a typical example of which is shown in FIG. 1. The DLL 10 includes a delay line 14, which, as explained in greater detail below, includes a large number of gates coupled to each other in series. The delay line 14 receives a reference clock signal CLKREF and generates an output clock signal CLKOUT having a delay relative to the reference clock signal CLKREF that is controlled by a delay control signal DelCtrl. The delay control signal DelCtrl adjusts the delay provided by the delay line 14 by altering the number of gates through which the CLKREF is coupled. The DLL 10 also includes a phase detector 16 and delay controller 18 coupled to outputs of the phase detector 16 for adjusting the delay of the delay line 14. The phase detector 16 compares the phase of the reference clock signal CLKREF to the phase of an output clock signal CLKOUT generated by delay line 14 to determine a phase error. The CLKOUT signal is thus used as a feedback clock signal, although other signals derived from the CLKOUT signal may instead be used as the feedback clock signal. The feedback clock signal is coupled to the input of phase detector though a model delay circuit 20. The model delay circuit 20 delays the feedback clock signal by substantially the sum of the input delay of the CLKREF signal being coupled to the phase detector 16 and the output delay of the CLKOUT signal being coupled from the delay line 14. As a result, the phase of the CLKOUT signal is accurately synchronized to the phase of the CLKREF signal. If the phase detector 16 is a digital phase detector, it typically generates an UP signal if the CLKOUT signal leads the CLKREF signal by more than a first phase error. The delay controller 18 responds to the UP signal by increasing the delay of the delay line 14 to reduce the phase error. Similarly, the phase detector 16 generates a DN signal if the CLKOUT signal lags the CLKREF signal by more than a second phase error. In that case, the delay controller 18 responds to the DN signal by decreasing the delay of the delay line 14 to again reduce the phase error. The phase detector 16 generates neither an UP signal nor a DN signal if the magnitude of the phase error is between the first phase error and the second phase error.
The DLL 10 can be used for a variety of functions in a memory device and in other integrated circuit devices. For example, the DLL 10 can be used in a memory device to perform such functions as synchronizing one signal, such as a data strobe signal DQS, to another signal, such as an external clock signal as long as a delay in coupling the external clock signal to the DLL10 and a delay in coupling the DQS signal from the DLL10 are compensated for by corresponding model delays in the feedback path of the DLL 10. The DQS signal can then be used to latch data at a time that is synchronized with the external clock signal.
The degree to which the DLL 10 is able to lock the phase of the CLKOUT signal to the phase of the CLKREF signal is largely determined by the delay adjustability of the delay line 14. If the delay of the delay line 14 can only be adjusted in relatively coarse steps, the error between the phase of the CLKOUT signal and the phase of the CLKREF signal can be relatively large. For this reason, it is desirable for the delay line 14 to have a large number of gates or other delay devices. A large number of gates or other delay devices allows the delay of the delay line to be adjusted in a larger number of steps. For example, if the delay line 14 has 72 delay stages, the delay line 14 can adjust the delay of the delay line in approximately 5 degree steps (i.e., (360° minus delay of model delay circuits)/72). Although a large number of gates or other delay devices provides a great deal of delay adjustablity, it can also result in a large power consumption.
In order to allow the delay of a delay line to be adjusted in relatively fine steps to provide high accuracy without consuming a significant amount of power, a phase mixer (not shown) can be used to interpolate between relatively coarse steps. Using a phase mixer, the CLKOUT signal is delayed relative to the CLKREF signal by the sum of the coarse steps provided by the delay line and fine steps provided by the phase mixer. Significantly, the minimum step size is then the size of a fine step.
Unfortunately, conventional DLLs using a combination of a delay line and a phase mixer to delay the CLKOUT signal relative to the CLKREF signal can suffer a number of performance limitations, primarily because the delay lines typically used have two inverting gates in each of a plurality of delay stages. As a result, the phase mixer must interpolate over a larger range in order to provide a given size of the fine step. Additionally, phase mixers interpolating over a large range often exhibit excessive non-linearity because the non-linearity of a phase mixer is normally a fixed percentage of the range over which the phase mixer interpolates. Thus, the larger coarse step provided by two inverting gates can result in an undesirable degree of non-linearity.
There is therefore a need for a delay line that provides good duty cycle symmetry, and that allows a phase mixer to interpolate over a relatively small range and provide good phase mixer linearity.